The present invention relates generally to memory operations occurring in computer systems, and more particularly to logic support for direct memory access (DMA) operations in a computer systems comprising a plurality of buses interconnected by bus bridges. Computer systems typically include more than one bus, each bus in the system having devices attached thereto which communicate locally with each other over the bus. System-wide communication over different buses is required, however, if a device attached to one bus needs to read or write information to or from a device on another bus. To permit system-wide communication between devices on different buses, bus-to-bus bridges (interfaces) are provided to match the communications protocol of one bus with that of another.
Known bus-to-bus bridges include those disclosed in the following co-pending patent applications assigned to the IBM Corporation: Application Ser. No. 07/815,992 entitled "BUS CONTROL LOGIC FOR COMPUTER SYSTEM HAVING DUAL BUS ARCHITECTURE"; U.S. Pat. No. 5,313,627 issued May 17, 1994 entitled "PARITY ERROR DETECTION AND RECOVERY"; Application Ser. No. 07/816,204 entitled "CACHE SNOOPING AND DATA INVALIDATION TECHNIQUE"; U.S. Pat. No. 5,255,374 issued Oct. 19, 1993 entitled "BUS INTERFACE LOGIC FOR COMPUTER SYSTEM HAVING DUAL BUS ARCHITECTURE"; entitled "BIDIRECTIONAL DATA STORAGE FACILITY FOR BUS INTERFACE UNIT"; Application Ser. No. 07/816,693 entitled "BUS INTERFACE FOR CONTROLLING SPEED OF BUS OPERATION"; U.S. Pat. No. 5,265,211 issued Nov. 23, 1993 entitled "ARBITRATION CONTROL LOGIC FOR COMPUTER SYSTEM HAVING DUAL BUS ARCHITECTURE"; and Application Ser. No. 07/816,698 entitled "METHOD AND APPARATUS FOR DETERMINING ADDRESS LOCATION AT BUS TO BUS INTERFACE", all filed on Jan. 2, 1992. These applications describe mechanisms which permit system-wide communication of devices attached to different buses in the system.
Each bus-to-bus bridge in a multi-bus computer system is used to connect two buses in the system. Various types of buses are available to construct a given computer system. Standard I/O buses include, for example, ISA or MICRO CHANNEL.RTM. ("MC-A") buses, which often are used to connect existing peripheral I/O devices to a system built around a more centralized, high performance bus.
One such high performance bus which is becoming widely accepted is the PCI (Peripheral Component Interconnect) bus, which is capable of performing significant data transfer in a relatively short period of time (up to 120 megabytes of data per second). The PCI bus achieves this high level of performance, in part, because it may be directly linked to other high speed buses, such as system buses to which a CPU may be connected, and thus may provide for rapid transfer of data between devices attached to the PCI bus and devices attached to the system bus. In fact, the operation of several high integration devices, such as certain graphics package controllers, require a direct link to a system bus through a high performance bus such as the PCI bus. In addition, the PCI bus architecture does not require any "glue logic" to operate peripheral devices connected to it. Glue logic for other buses typically consists of miscellaneous hardware components such as decoders, buffers or latches that are installed intermediate the peripheral devices and the bus.
The primary PCI bus operates on a synchronous clock signal of 33 MHz, and the strings of data transmitted over the PCI bus are 32 bits long. A 32-bit data string on the PCI bus is called a double word (DWORD), which is divided into 4 bytes each comprised of 8 bits of data. The address and data information carried by the PCI bus are multiplexed onto one signal. Multiplexing eliminates the need for separate address and data lines, which in turn, reduces the amount of signals required in a PCI bus environment as opposed to other bus architectures. The number of signals required in PCI bus architecture is between 45-47 while non-multiplexed buses typically require twice this number. Accordingly, because the number of signals are reduced, the number of connection pins required to support a device linked to the PCI bus is also reduced by a corresponding number. PCI architecture is thus particularly adapted for highly integrated desktop computer systems.
A more detailed description of the structure and operation of PCI bus architecture is provided in "Peripheral Component Interconnect (PCI) Revision 2.0 Specification", published Apr. 30, 1993; "Preliminary PCI System Design Guide" revision 0.6, published Nov. 1, 1992, and "Peripheral Component Interconnect (PCI) Add-in Board/Connector Addendum", (Draft) published 6 Nov. 1992; all by the PCI Special Interest Group, the contents of which references are incorporated herein by reference as if they were fully set forth.
Interfacing the PCI bus to standard I/O buses in a computer system is problematic, however, if the communications protocols between the PCI bus and the standard I/O bus are different. For example, direct memory access (DMA) cycles may be handled differently by devices attached to the PCI bus as compared to those connected to a standard I/O bus. DMA cycles are operations in which data is transferred between system memory and input/output units by a DMA controller without intervention by the CPU. Most devices which attach directly to the PCI bus are generally high performance 32-bit bus master devices which have their own built-in DMA control logic. Such bus master devices need not rely on a system-provided DMA controller, thereby permitting the device to initiate a DMA transfer by itself instead of relying on the system DMA controller to initiate data transfers. A DMA slave device is typically lower performance, less expensive and requires the assistance of a system DMA controller to perform a DMA transfer.
Examples of typical DMA slave devices are serial port, parallel port, and floppy disk devices. In order to maintain both hardware and software compatibility with any system which contains a standard I/O bus such an ISA or MC-A bus, it is required that these standard I/O devices, as well as a standard system DMA controller, exist in the system. DMA controllers may be of ISA or PS2 architecture. Although ISA and PS2 DMA controllers are slightly different, they both require specific sets of signals in order to control arbitration and data transfers. A DMA controller is required to maintain compatibility with existing hardware (I/O devices), and ISA/PS2 architecture is required to maintain compatibility with existing software.
DMA controllers have specific functions requiring arbitration, bus sizing, DMA cycles (e.g. transfer timings and terminal count), and various modes (e.g. single/burst/demand/cascade) of operation. The DMA controller is typically located on the standard I/O bus, which precludes systems from being built without a standard I/O bus. The PCI bus does not provide signals or support for a system having a DMA controller located on the PCI bus.
I/O devices on a standard I/O bus are likely to be less performance-oriented than devices attached to the PCI bus and more likely to require the assistance of a DMA controller to perform DMA cycles (e.g., 8, 16 or 32-bit I/O devices having no DMA controller built-in). A DMA controller requires dynamic bus sizing when managing DMA cycles for different types of slave devices, meaning that it needs to know the size (8-bit, 16-bit, etc.) of the particular slave device on whose behalf it is managing a DMA cycle. Such dynamic bus sizing is typically supported on standard I/O buses, such as the AT.RTM., ISA or MICROCHANNEL.RTM. buses.
Because the PCI bus was not architected with such dynamic bus sizing capability, however, the PCI bus cannot support DMA cycle operations involving DMA slave devices. DMA slave devices which are attached to a standard I/O bridge which is in turn connected to a PCI bus, then, cannot have DMA operations performed on their behalf by a DMA controller over the PCI bus. Such operations are necessary, however, if the multi-bus system architecture requires DMA slave devices on the standard I/O bus to cross over the PCI bus to access system memory.
It is an object of the present invention, then, to provide a mechanism for supporting DMA cycles for DMA slave devices on a standard I/O bus which is attached to a high performance bus (such as a PCI bus) by means of a standard bus bridge, in order to permit a DMA controller to perform DMA cycles on behalf of the slave devices over the PCI bus to system memory. The mechanism is provided by defining a sideband interface to a standard I/O bridge which allows a system DMA controller to always exist on the PCI bus. By utilizing the sideband interface, DMA slave devices on an optional expansion bus can also be supported. In addition, the DMA specific sideband signals may be multiplexed with existing sideband signals.